2021 Virtual Undergraduate Research Symposium

2021 Virtual Undergraduate Research Symposium

Using Error Divisible Gates for AFM Heisenberg Model with VQE

Using Error Divisible Gates for AFM Heisenberg Model with VQE

PROJECT NUMBER: 88 | AUTHOR: Paul Varosy, Physics

MENTOR: Eliot Kapit, Physics


Current quantum computers typically have a fixed native gate set to perform quantum operations: a two qubit entangling gate and single qubit rotations. Algorithms commonly call for partial two qubit rotations, requiring two or three native two qubit gates; a significant overhead which proliferates error. By optimizing gates at the hardware level, we can implement fractional gates natively. If this tuning is done cleverly, as in error divisible gates (EDG), we see an error rate which decreases with the fraction of a full gate. We then apply EDG in a variational quantum eigensolver (VQE) calculation to approximate the ground state energy of the antiferromagnetic (AFM) Heisenberg model. Using classical simulation, we compare EDG to existing gate models, demonstrating its superior ability to approximate the ground state when using error rates taken from current superconducting qubit hardware.



Paul Varosy is a Sophomore in Engineering Physics working towards a Quantum Engineering minor. His freshman year, he participated in the FIRST research fellowship, providing many of the prerequisite skills to succeed in research. He spent the following summer performing research with Professor Eliot Kapit in the Physics department, and continued to work with the group during the school year. His current research has been in simulating novel NISQ algorithms in the presence of noise. In the future, Paul aims to continue to research in the vast field of quantum information.


  1. Hi Paul, this is a great poster and a very interesting topic! Could you dive into the benefits of implementing these gates at the hardware level, and why it might be more optimal to do so in hardware than in software?

    • Hi Zoe, by implementing fractional gates at the hardware level, it enables the vastly decreased error rates for these widely used gates. The increased percentage of ground state energy from the VQE calculation when using EDG demonstrates just how powerful optimizing these gates at a hardware level can be, as we see an increase from <60% to ~75%-80%.

      When considering superconducting qubits, the specific reason for this decreased error is that gates are enacted by sending microwave pulses to the qubits. When we optimize a fractional gate at the hardware level, we are specifically tuning the precise shape and total duration of the microwave pulse. My collaborator David spent time optimizing these pulses and found that for fractional gates, the total duration of the pulse can be much shorter and still achieve the gate, which decreases error. This work is currently still in preparation, but he gave a talk on this at the APS March Meeting (C33: Error-divisible two-qubit quantum gates) if you are interested in a more in-depth explanation.

      The advantage to just using software is that then an engineer only needs to a single pulse for the fixed two-qubit gate rather than having to optimize the pulse for every fractional gate implemented. I hope this answers your question!

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